1. Field of the Invention
This invention relates to a method for controlling the thickness of a passivation layer on a semiconductor device, and particularly relates to a method using only one photo mask for controlling the thickness of a passivation layer underlying with a fuse on a dynamic random access memory.
2. Description of the Prior Art
Redundant cells can be added to a memory design to replace defective cells, which are identified by an electrical test after wafer processing. Fuses incorporated on the wafer can be blown by the incident laser energy to swamp defective cells, so redundant cells are widely used in fabricating the semiconductor device.
In fabricating the memory cell, a passivation layer such as CVD silicon oxide or plasma enhanced CVD silicon nitride is laid down on the wafer surface. This passivation layer seals the device structures on the wafer from contaminants and moisture, and also serves as a scratch protection layer. The passivation layer is deposited over the entire chip surface of the wafer to protect the devices in the wafer. This is an insulating, protective layer that prevents mechanical and chemical damage during assembling and packaging.
As shown in FIG. 1, a cross-sectional view of a typical wafer of a memory cell with an embedded fuse in the wafer. The layers are, from bottom to top, as follows. The field oxide layer 1 formed on the Si-substrate is about 2150 angstroms in thickness, the thickness of the TEOS oxide layer 2 formed on the field oxide layer 1 is about 1000 angstroms. The thickness of the IPO1 (Inter poly-Si Oxide) BPSG layer 3 formed on the TEOS oxide layer 2 is about 5100 angstroms, and the IPO1-1 BPSG layer 4 formed on the IPO1 BPSG layer 3 is about 1000 angstroms in thickness.
The thickness of the poly-2 fuse layer 5 formed on the IPO1-1 BPSG 4 is about 1500 angstroms in thickness, the IPO2 BPSG layer 6 formed on the poly-2 fuse layer 5 is about 4000 angstroms in thickness. The ILD (Inter Layer Dielectric) layer 7 formed on the IPO2 BPSG layer 6 is about 11000 angstroms in thickness, and the metal barrier Ti layer 8 formed on the ILD layer 7 is about 1000 angstroms in thickness. The TiN layer 9 formed on the Metal barrier Ti layer 8 is about 600 angstroms in thickness, and the first metal layer 10 is formed on the TiN layer 9. The first anti-reflective coating 11 formed on the first metal layer 10 is about 300 angstroms, and the anti-reflective coating 11 is used to improve the precision of alignment in exposing the first metal layer 10. The thickness of the IMD (Inter Metal Dielectric) layer 12 formed on the first anti-reflective coating 11 is about 11000 angstroms in thickness. The first metal layer 10 is usually made of the AlCu alloy, and the first anti-reflective coating 11 is frequently formed of TiN in the prior art method of fabricating memory cells.
Next, the photoresist is applied on the topography of the wafer and is developed to form the photoresist mask by using photo mask (not shown). Then the photoresist pattern 13 is formed and the oxide etchant 14 is used to etch the portion of the IMD layer that is not covered by the photoresist pattern 13 to fabricate the via contact 15 and the fuse window 19 simultaneously. The ILD layer 7 as well as the IPO2 BPSG layer 6 are etched in the forgoing etching step. According to the prior art of forming the via contact 15, the recipe used to etch the IMD layer 12 is the etchant including C.sub.4 F.sub.8, CF.sub.4, Ar and CHF.sub.3. In order to remove a portion of the first anti-reflective coating 11, the etchant including C.sub.4 F.sub.8, CF.sub.4, Ar and CHF.sub.3 are used to etch the portion of the first anti-reflective coating 11. When the Ar together with the C.sub.4 F.sub.8, CF.sub.4 and CHF.sub.3 are used as the oxide etchant 14 to etch the first anti-reflective coating 11, the etching rate of the exposed oxide is about 5000-6000 angstroms per minute. Because the momentum of the Ar in etching the first anti-reflective coating 11 is very large, so that the atoms in the first anti-reflective coating 11 will be removed, and the oxide loss of the IMD layer 12 is more than about 5000 angstroms in thickness. As noted that, in fabricating the via contact 15 and the fuse window 19 simultaneously using one etching step, the oxide loss due to the traditional recipe gives rise to a problem of controlling the thickness of the oxide fuse window 19.
In the other respect, when the wafer is used to fabricate the structure mentioned above with a raised fuse, the cross sectional view of the wafer is similar to the structure of the wafer shown in FIG. 1. The cross sectional view of the portion of wafer shown in FIG. 2A is for containing a raised fuse, and the cross sectional view of the portion of wafer shown in FIG. 2B is for fabricating the bonding pad. A mask called the "pad mask" or "bonding contact mask" is used to define patterns corresponding to the regions in which electrical contact to the finished circuit will be made. These patterns in a resist layer allow openings in the passivation layer to be etched down to metal areas on the circuit called "bonding pads." Openings are etched into the passivation layer so that a set of metallization patterns under the passivation layer is exposed. These metal patterns are normally located in the periphery of the circuit and are called bonding pads. Wires are connected (bonded) to the metal of the bonding pads and are also bonded to the chip package.
The cross-sectional views of the portions of the wafer shown in FIGS. 2A and 2B illustrate the wafer with the raised fuse when etching the second anti-reflective coating 30 (FIG. 2B) on the metal pattern. The second anti-reflective coating 30 is on the second metal layer 29 (FIGS. 2A and 2B), and the function of the second anti-reflective coating 30 is the same as that of the anti-reflective coating 11 shown in FIG. 1. The portion of the wafer shown in FIG. 2A has a field oxide layer 20 on the Si substrate. The IPO (Inter Poly Oxide) layer 21 is formed on the field oxide layer 20 and the Si substrate. The ILD (Inter Layer Dioxide) layer 22 is formed on the IPO layer 21; the first metal layer 23 is patterned on the ILD layer 22, and the IMD (Inter Metal Dioxide) layer 24 is formed on the patterned first metal layer 23. Subsequently, the second metal layer 29 and the second anti-reflective coating 30 are patterned on the IMD layer 24.
Next, the silicon nitride layer 39 is deposited on the topography of the wafer, and then the polyimide layer 42 is patterned on the wafer. Subsequently, the patterned polyimide layer 42 is used as a mask when using silicon nitride etchant CF.sub.4, CHF.sub.3, and Ar together with N.sub.2 as an etchant 45, which is similar to an oxide etchant, to etch the silicon nitride layer 39. As shown in FIGS. 2A and 2B, the exposed silicon nitride layer 39 is removed, and the spacer 47 is formed on the side walls of the raised fuse. The etching step in FIG. 2A and FIG. 2B is performed simultaneously. In order to form the bonding pad, as shown in FIG. 2B, the second anti-reflective coating 30 on the second metal layer 29 must be removed thoroughly. So the etching step using an etchant including CF.sub.4, CHF.sub.3, and Ar together with N.sub.2 is performed to overetch for additional one minute. So at least 5000 angstroms of the oxide layer in the IPO layer 21 is removed by the etching loss.
The oxide layer above the embedded poly-2 fuse layer 5 shown in FIG. 1 must be maintained greater than 4500 angstroms, but the etching step using the traditional etchant presents difficulties in controlling the thickness of the oxide layer above the buried poly-2 fuse layer 5. Besides, the oxide loss resulting from the etching step using the traditional etchant cannot control the thickness of the oxide layer because the second anti-reflective coating 30 in FIG. 2B must be thoroughly removed. Oxide loss must be carefully controlled. On the other hand, to ensure the thoroughly removal of the anti-reflective coating (TiN layer), the over-etching step using traditional etchant must be utilized. So, control of the thickness of the oxide layer in the passivation layer is very difficult.